The present invention relates to semiconductor integrated circuits and, more particularly, to integrated circuits having scannable dynamic logic elements and to a method of inserting a scan chain in a latch-less data path.
Semiconductor integrated circuits, such as application specific integrated circuits (ASICs), often incorporate thousands of semiconductor elements on a single chip. There are two primary types of digital circuits, static logic and dynamic logic. Static logic does not require periodic clock signals to maintain voltage levels at the various nodes within the circuit. Logical functions are typically separated by sequential elements, such as latches and other flip-flop devices, which define clock boundaries within individual signal paths. Dynamic logic data paths can be latch-less, and require periodic clock signals to maintain or refresh voltage levels. Dynamic logic circuits are usually faster and may consume more power than static logic circuits, but are more difficult to design and are more sensitive to timing errors and noise.
Once a digital circuit has been fabricated, the logical function and the timing of individual signal paths between the elements are tested according to a variety of test methodologies. One common test methodology for static logic is referred to as "scan testing". Scan testing is implemented by converting selected sequential elements into scannable elements by adding extra logic and a multiplexer. Each scannable element selects data from a normal data input or a test data input based on a test enable signal. The scannable elements are connected together to form a scan chain by connecting the output of each scannable element to the test data input of the next, subsequent scannable element in the chain.
When the test enable signal is activated, the scannable elements switch from the normal data flow mode to the scan mode. Each scannable element is controlled to select data from the test data input as opposed to the normal data input. A test vector is then loaded into the scannable elements by serially shifting the test vector through the scan chain. After the test vector is loaded, the test enable signal is deactivated and the scannable elements switch from the scan mode to the normal data flow mode. After a selected number of clock cycles, the test signal is again activated. The resulting data that is stored in each of the scannable elements forms an output vector which scanned out through the scan chain and compared with an expected output vector. Errors in the logical function or timing are detected by detecting discrepancies between the actual output vector and the expected output vector. One of the disadvantages of scan testing is that the extra logic required to implement the multiplexer function in each of the scannable elements adds at least a gate delay to the signal path.
With conventional dynamic logic, sequential elements such as registers and latches must be inserted into the data paths to create clock boundaries for the scan chain. However, the sequential elements also add delay to the data paths, which may negate the speed advantages of using dynamic logic.